In non-clock-forwarded communications systems, data streams are transmitted to receivers without transmitting separate, distinct clock signals. In such systems, a receiver can perform clock-and-data-recovery (CDR) processing to recover a clock signal from each data stream, where the clock signal is derived based on the timing of the data represented in the data stream. A typical CDR circuit comprises a sampling clock generator, such as a phase-locked loop (PLL) or a delay-locked loop (DLL), that generates one or more sampling clocks used to sample the received data stream. In some communications systems, a single receiver may receive multiple, different data streams, potentially having different data rates. Such a receiver will typically have a different CDR circuit for each different data stream. Implementing multiple CDR circuits, each with its own sampling clock generator can require too much layout area and/or operating power for some integrated circuit applications.